1. Field of the Invention
The present invention relates to a logic circuit, and more specifically to a field effect transistor (FET) logic circuit.
2. Description of Related Art
In the prior art, a fundamental circuit called a direct coupled FET logic (abbreviated to "DCFL") is widely known as a low power consumption logic circuit. This circuit is explained in many publications including FIG. 7.16 on Page 251 in "Ultra High Speed Compound Semiconductor Device", supervised by S. Sugano, published by Baitukan K. K., Nov. 30, 1986.
Referring to FIG. 1, there is shown a circuit diagram of one example of a DCFL circuit in the prior art. As shown in FIG. 1, the shown DCFL circuit is an inverter which includes a depletion compound semiconductor MES (metal-semiconductor) FET 1 having a drain connected to a first power supply terminal 31 (V.sub.DD) and a gate and a source connected in common at a node 41 to a drain of an enhancement compound semiconductor MES FET 2. A gate of this enhancement FET 2 is connected to a second power supply terminal 32 (namely, a ground voltage V.sub.SS). The node 41 is connected to an output terminal 22. In this DCFL circuit, the enhancement FET 2 operates as a switching device, and the depletion FET 1 operates as a load.
With this arrangement, if a low level is applied to the input terminal 21, the enhancement FET 2 is turned off, so that the potential of the output terminal 22 elevates to the power supply voltage V.sub.DD. On the other hand, if a high level is applied to the input terminal 21, the enhancement FET 2 is turned on, so that the potential of the output terminal 22 drops. At this time, the output potential of the output terminal 22 is determined by a current capability of the depletion FET 1 and a current capability of the enhancement FET 2. In any case, the output potential of the output terminal 22 never drops to the potential V.sub.SS given by the second power supply terminal 32.
Incidentally, Japanese Patent Application Pre-examination Publication Nos. JP-A-01-222484 and JP-A-09-261038 (an English abstract of these Japanese patent publications are available and the content of those English abstracts are incorporated by reference in its entirety into this application) disclose different DCFL circuits. As described in these Japanese patent publications and the above referred literature, it is known that the power consumption of the logic circuit can be reduced by using the DCFL circuit.
In the above mentioned prior art circuit, the high level output potential reaches the power supply voltage V.sub.DD. Therefore, considering that the output terminal 22 is connected to a gate of an input enhancement MES FET (not shown) of a next stage logic circuit (not shown), the high level output potential exceeds a potential which turns on a gate-source of the input enhancements MES FET of the next stage logic circuit, with the result that a current flows from the output terminal through the gate of the input enhancement MES FET of the next stage logic circuit to the source of the input enhancement MES FET of the next stage logic circuit. This gate potential for turning on the gate-source of the MES FET will be called a gate turn-on voltage in this specification, and is higher than a gate potential of the MES FET for turning on the MES FET, namely for turning a drain-source channel of the MES FET. Because of this, in the prior art circuit, when the power supply voltage is greater than the gate turn-on voltage of the MES FET, the power consumption becomes large in the high level outputting condition.
In addition, in the above mentioned prior art circuit, the low level of the output voltage never drops to the potential of the second power supply voltage (ground), but becomes on the order of plus several 100 mV. At this time, since the threshold of an enhancement FET is at a similar level, the input enhancement FET of the next stage logic circuit cannot be put in a complete OFF condition. Namely, in the next stage logic circuit, a current flows through a drain-source channel of the input enhancement FET, with the result that the consumed current resultantly increases. In other words, in this prior art circuit, when the low level is outputted, the next stage input enhancement FET is not put in the complete OFF condition, so that the power consumption becomes increased.
The above mentioned problems cannot be overcome even by technologies disclosed in the above referred Japanese patent publications